Device Characteristics and Equivalent Circuits for NMOS Gate-to-Drain Soft and Hard Breakdown in Polysilicon/SiON Gate Stacks

In state-of-the-art technologies, the currents in all n-channel field-effect transistor device terminals can be severely degraded when a soft or hard dielectric breakdown event occurs from gate-to-drain. The equivalent circuits that are commonly used for modeling gate-to-drain breakdown do not adequately capture all of the salient features of post breakdown device characteristics and can yield results that are overly optimistic. We present an equivalent circuit comprehending both soft and hard breakdown that can be used to accurately model gate, drain, and source currents following a breakdown event from gate-to-drain.