Title :
A Highly Punchthrough-Immune Array Architecture and Program Method for Floating-Gate NOR-Type Nonvolatile Memory
Author :
Tsai, Wen-Jer ; Ou, Tien Fan ; Cheng, Cheng-Hsien ; Lu, Chun-Yuan ; Huang, J.S. ; Yan, S.G. ; Cheng, C.C. ; Tsai, Ping Hung ; Hung, C.S. ; Chu, T.K. ; Yih, C.M. ; Lu, Tao Cheng ; Chen, Kuang-Chao ; Lu, Chih-Yuan
Author_Institution :
Macronix Int. Co., Hsinchu, Taiwan
fDate :
4/1/2011 12:00:00 AM
Abstract :
A novel array architecture is proposed for floating-gate nor-type nonvolatile memory cells. By embedding a floating n+ region between two cells in each memory pair, punchthrough (PT) immunity is greatly improved. Since the operating cell and the cascade cell belong to two independent word-lines, bit-pattern effect on read and program characteristics is mitigated, and multilevel-cell storage can be easily realized. No additional program disturb has been found. Erase, endurance, and retention characteristics are comparable with its conventional counterpart. According to simulations, Lg as short as 56 nm, which is projected to serve for 28 nm technology node, is feasible without suffering a serious PT effect.
Keywords :
NOR circuits; random-access storage; bit-pattern effect; cascade cell; endurance characteristics; erase characteristics; floating-gate NOR-type nonvolatile memory cells; independent wordlines; multilevel-cell storage; operating cell; program method; punchthrough-immune array architecture; read characteristics; retention characteristics; size 28 nm; size 56 nm; Arrays; Current measurement; Leakage current; Logic gates; Microprocessors; Synthetic aperture sonar; Bit-pattern effect; cascade cell; channel-hotelectron (CHE) injection; floating diffusion region; floating gate (FG); independent wordline (WL); nonvolatile memory; nor flash; punchthrough (PT); transient charging current; virtualground (VG) array;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2011.2104960
