Estimation of propagation delay considering short-circuit current for static CMOS gates

We present a formula of propagation delay for static CMOS logic gates considering short-circuit current and current flowing through gate capacitance and using the nth power law MOSFET model which considers velocity saturation effects. The short circuit current is represented by a piecewise linear function, which enables detailed analysis of the transient behaviour of a CMOS inverter. We found that the error of our formulas for a CMOS inverter is less than 8% from circuit simulation in most cases of our experiments. We also applied these formulas to logic gates made up of series-parallel connected MOSFETs by replacing the series-connected MOSFETs with an equivalent MOSFET. The influence of short-circuit power on delay, which is explicitly modeled in our formula, is numerically demonstrated such that the influence becomes large with slow input transition and small output load capacitance