Title :
A 1.5 V, 4.1 mW dual-channel audio delta-sigma D/A converter
Author :
Fujimori, Ichiro ; Sugimoto, Tetsuro
Author_Institution :
AMK DesignTek, San Diego, CA, USA
fDate :
12/1/1998 12:00:00 AM
Abstract :
The paper describes a stereo digital-to-analog converter intended for portable digital-audio which operates at 1.5 V and consumes only 4.1 mW. A 15-level quantization, third-order delta-sigma was employed to reduce digital operation speed, relax out-of-band filtering requirements, and enhance immunity to clock jitter. The use of direct charge transfer switched-capacitor technique in the multibit reconstruction DAC reduces kT/C noise and element mismatch without increase of power dissipation. The data weighted averaging algorithm suppresses nonlinearity caused by capacitor mismatch by first-order noise-shaping, thereby making mismatch-induced noise negligible. The stereo audio DAC achieves 90 dB dynamic range and 81 dB peak signal-to-noise-plus-distortion ratio over a 20 kHz passband. The 5.3 mm 2 chip is fabricated in a 0.6 μm CMOS technology which includes low-threshold devices
Keywords :
CMOS integrated circuits; audio discs; audio signal processing; delta-sigma modulation; low-power electronics; switched capacitor networks; timing jitter; 0.6 micron; 1.5 V; 15-level quantization; 4.1 W; CMOS technology; audio delta-sigma DAC; capacitor mismatch; clock jitter immunity; data weighted averaging algorithm; direct charge transfer SC technique; dual-channel D/A converter; first-order noise-shaping; low-threshold devices; mismatch-induced noise; multibit reconstruction DAC; nonlinearity suppression; portable digital-audio; stereo digital-to-analog converter; switched-capacitor technique; third-order delta-sigma; CMOS technology; Charge transfer; Clocks; Digital filters; Digital-analog conversion; Filtering; Jitter; Noise reduction; Power dissipation; Quantization;
Journal_Title :
Solid-State Circuits, IEEE Journal of
