Title :
A third-order Δ-Σ modulator using second-order noise-shaping dynamic element matching
Author :
Yasuda, Akira ; Tanimoto, Hiroshi ; Iida, Tetsuya
Author_Institution :
Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan
fDate :
12/1/1998 12:00:00 AM
Abstract :
A multibit Δ-Σ modulator is an attractive way of realizing a high-accuracy, high-speed, and low-power data converter. However, the overall resolution of the modulator is determined by the internal digital-to-analog conversion (DAC) linearity. Methods for high-order noise shaping, noise-shaping dynamic element matching (NSDEM), have been proposed in order to overcome this drawback. However, a real implementation has not been realized until now. This paper presents the actual circuit configuration of a tree-structured NSDEM (TNSDEM) technique, which is applied to a multibit Δ-Σ DAC and analog-to-digital converter (ADC) using a nine-level internal DAC. This is the first report of a Δ-Σ ADC and DAC using the second-order NSDEM method. The test chip of the third-order Δ-Σ ADC realizes a signal bandwidth of 100 kHz and a dynamic range of 79 dB in the ADC and 80 dB in the DAC. The test chip only consumes 9.6 mW in the ADC and 5.2 mW in the DAC with a 2.7 V power supply
Keywords :
CMOS integrated circuits; analogue-digital conversion; circuit feedback; delta-sigma modulation; integrated circuit noise; Δ-Σ ADC; 100 kHz; 2.7 V; 5.2 mW; 9.6 mW; digital-to-analog conversion linearity; dynamic element matching; high-speed data converter; internal DAC linearity; low-power data converter; multibit Δ-Σ modulator; nine-level internal DAC; second-order noise-shaping; third-order Δ-Σ modulator; tree-structured NSDEM technique; Analog-digital conversion; Bandwidth; Circuit testing; Delta modulation; Digital modulation; Digital-analog conversion; Dynamic range; Linearity; Noise shaping; Power supplies;
Journal_Title :
Solid-State Circuits, IEEE Journal of