Title :
A 400-Msample/s, 6-b CMOS folding and interpolating ADC
Author :
Flynn, Michael P. ; Sheahan, Ben
Author_Institution :
DSPS R&D Lab., Texas Instrum. Inc., Dallas, TX, USA
fDate :
12/1/1998 12:00:00 AM
Abstract :
A 400-Msample/s, 6-bit CMOS folding and interpolating analog-to-digital converter (ADC) is described. A low-impedance current-mode approach is adopted. Current-division interpolation incorporated within the folders allows fast operation and is compatible with low supply voltages. This interpolation scheme, together with a short aperture comparator, gives good performance for input frequencies up to one-quarter of the sampling rate without using a sample and hold. For simplicity, the ADC uses only a single clock and its complement. The device is implemented in a 0.5 μm BiCMOS technology using only CMOS devices. The converter occupies 0.6 mm2 and dissipates 200 mW from a 3.2 V supply
Keywords :
CMOS integrated circuits; analogue-digital conversion; interpolation; 0.5 micron; 200 mW; 3.2 V; 6 bit; BiCMOS technology; CMOS folding ADC; analog-to-digital converter; current-division interpolation; interpolating ADC; interpolation scheme; low-impedance current-mode approach; short aperture comparator; single clock configuration; Analog-digital conversion; Apertures; BiCMOS integrated circuits; CMOS technology; Clocks; Energy consumption; Instruments; Interpolation; Low voltage; Sampling methods;
Journal_Title :
Solid-State Circuits, IEEE Journal of
