A 12-bit intrinsic accuracy high-speed CMOS DAC

Author

Bastos, Jose ; Marques, Augusto M. ; Steyaert, Michel S J ; Sansen, Willy

Author_Institution

Katholieke Univ., Leuven, Belgium

Volume

33

Issue

12

fYear

1998

fDate

12/1/1998 12:00:00 AM

Firstpage

1959

Lastpage

1969

Abstract

A 12-bit intrinsic accuracy digital-to-analog (D/A) converter integrated in a standard digital 0.5 μm CMOS technology is presented. It is based on a current steering doubly segmented 6+2+4 architecture and requires no calibration, no trimming, or dynamic averaging. The differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 and 0.6 least significant bits (LSB´s), respectively. The measured glitch energy is 1.9 pV.s. For a 12-bit resolution, the converter reaches an update rate of 300 MS/s. By reducing the voltage supply of the latches to 2.0 V, the glitch energy is reduced to sub-pV.s, and the update rate reaches 500 MS/s, for a resolution of 8 bits. The worst case power consumption is 320 mW, and it operates from a single 3.3 V voltage supply. The die area is 3.2 mm²

Keywords

CMOS integrated circuits; digital-analogue conversion; high-speed integrated circuits; integrated circuit design; 0.5 micron; 12 bit; 3.3 V; 320 mW; current steering doubly segmented 6+2+4 architecture; differential nonlinearity; digital-to-analog converter; high-speed CMOS DAC; integral nonlinearity; CMOS digital integrated circuits; CMOS technology; Calibration; Decoding; Energy consumption; Energy measurement; Energy resolution; Latches; Signal resolution; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.735536

Filename

735536