A delta-sigma PLL for 14-b, 50 kSample/s frequency-to-digital conversion of a 10 MHz FM signal

In many wireless applications, it is necessary to demodulate and digitize frequency or phase modulated signals. Most commonly, this is done using separate frequency discrimination and analog-to-digital (A/D) conversion. In low-cost IC technologies, such as CMOS, precise analog frequented discrimination is not practical, so the A/D conversion is usually performed in quadrature or at a nonzero intermediate frequency (IF) with digital frequency discrimination. While practical, the approach tends to require complicated A/D converters, and accuracy is usually limited by the duality of the A/D conversion. This paper presents an alternative structure, referred to as a delta-sigma frequency-to-digital converter (ΔΣFDC), that simultaneously performs frequency demodulation and digitization. The ΔΣFDC is shown to offer high-precision performance with very low analog complexity. A prototype of the key component of the ΔΣFDC has been fabricated in a 0.6 μm, single-poly, CMOS process. The prototype achieved 50 kSample/s frequency-to-digital conversion of a 10 MHz frequency-modulated signal with a worst case signal-to-noise-and-distortion ratio of 85 dB and a worst case spurious-free dynamic range of 88 dH