• DocumentCode
    1450023
  • Title

    A CMOS transceiver for 10-Mb/s and 100-Mb/s Ethernet

  • Author

    Everitt, James ; Parker, James F. ; Hurst, Paul ; Nack, Dave ; Konda, Kishan Rao

  • Author_Institution
    Level One Commun., Sacramento, CA, USA
  • Volume
    33
  • Issue
    12
  • fYear
    1998
  • fDate
    12/1/1998 12:00:00 AM
  • Firstpage
    2169
  • Lastpage
    2177
  • Abstract
    A CMOS IC that implements the 802.3 Ethernet standards for 10- and 100-Mb/s data rates is described. The circuit uses mixed-signal techniques to perform transmit pulse shaping, receive adaptive line equalization, baseline wander compensation, and timing recovery. The IC occupies 23 mm2 in a 0.6-μm single-poly CMOS process and dissipates 850 mW from a 5-V supply
  • Keywords
    CMOS integrated circuits; local area networks; mixed analogue-digital integrated circuits; transceivers; 0.6 micron; 10 Mbit/s; 100 Mbit/s; 5 V; 850 mW; CMOS transceiver; Ethernet; baseline wander compensation; mixed signal IC; receive adaptive line equalization; single-poly CMOS process; timing recovery; transmit pulse shaping; ANSI standards; Adaptive equalizers; CMOS integrated circuits; Coaxial cables; Ethernet networks; FDDI; Protocols; Standards development; Timing; Transceivers;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.735701
  • Filename
    735701
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1450023