DocumentCode :
1450511
Title :
The effects of boron penetration on p+ polysilicon gated PMOS devices
Author :
Pfiester, James R. ; Baker, Frank K. ; Mele, Thomas C. ; Tseng, Hsing-Hung ; Tobin, Philip J. ; Hayden, James D. ; Miller, James W. ; Gunderson, Craog D. ; Parrillo, L.C.
Author_Institution :
Motorola Inc., Austin, TX, USA
Volume :
37
Issue :
8
fYear :
1990
fDate :
8/1/1990 12:00:00 AM
Firstpage :
1842
Lastpage :
1851
Abstract :
The penetration of boron into and through the gate oxides of PMOS devices which employ p+ doped polysilicon gates is studied. Boron penetration results in large positive shifts in VFB , increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF2 implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi2 salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO 2/Si interface
Keywords :
boron; insulated gate field effect transistors; integrated circuit technology; ion implantation; silicon; silicon compounds; B penetration effects; BF2 implantations; F related effects; MOSFETs; P coimplant; PMOS devices; PMOS threshold voltage instabilities; Si polycrystalline gates; SiO2-Si interface; TiSi2 salicide; electron trapping rate; flatband voltage shifts; fully-depleted p-type layer; gate implantation; interface trap density; low-field mobility; p+ polysilicon gated PMOS devices; polysilicon gate; shifts in VFB; subthreshold slope; Annealing; Boron; Electron mobility; Electron traps; Fabrication; Implants; MOS devices; Silicon; Temperature; Threshold voltage;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.57135
Filename :
57135
Link To Document :
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