DocumentCode
1450704
Title
An optically delineated 4.2-μm2 self-aligned isolated-plate stacked-capacitor DRAM cell
Author
Kimura, Shin-ichiro ; Kawamoto, Yoshifumi ; Hasegawa, Norio ; Hiraiwa, Atsushi ; Nakagome, Yoshinobu ; Aoki, Masakazu ; Kisu, Teruaki ; Sunami, Hideo ; Itoh, Kiyoo
Author_Institution
Hitachi Ltd., Tokyo, Japan
Volume
35
Issue
10
fYear
1988
fDate
10/1/1988 12:00:00 AM
Firstpage
1591
Lastpage
1595
Abstract
A 4.2-μm2 stacked-capacitor DRAM (dynamic random-access memory) cell was achieved using conventional i-line photolithography that realizes 0.6-μm pattern delineation. To obtain sufficient stored charge for memory operation, self-aligned plate-isolation technology, a novel pattern-enlargement method named peripherally added resist lithography (PEARL), and a highly reliable ultrathin capacitor dielectric film were developed. These technologies enable a stored charge of 25 fF/b (41 fC/b) in the present cell. Charge-retention characteristics and alpha-particle immunity are favorable, indicating that this cell is a good candidate for application to 16-Mb DRAMs
Keywords
VLSI; integrated memory circuits; photolithography; random-access storage; 0.6 micron; 16 Mbit; alpha-particle immunity; charge-retention characteristics; conventional i-line photolithography; pattern delineation; pattern-enlargement method; peripherally added resist lithography; self-aligned isolated-plate stacked-capacitor DRAM cell; self-aligned plate-isolation technology; ultrathin capacitor dielectric film; Capacitance; Capacitors; Dielectric films; Fabrication; Isolation technology; Lithography; Optical films; Random access memory; Resists; Very large scale integration;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.7358
Filename
7358
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