• DocumentCode
    1450821
  • Title

    Two-Step Write Scheme for Reducing Sneak-Path Leakage in Complementary Memristor Array

  • Author

    Jung, Chul-Moon ; Choi, Jun-Myung ; Min, Kyeong-Sik

  • Author_Institution
    Sch. of Electr. Eng., Kookmin Univ., Seoul, South Korea
  • Volume
    11
  • Issue
    3
  • fYear
    2012
  • fDate
    5/1/2012 12:00:00 AM
  • Firstpage
    611
  • Lastpage
    618
  • Abstract
    In this paper, a new two-step write scheme is proposed to minimize sneak-path leakage in complementary memristor (CM) array, where no selection device is needed. When R RESET/R SET = 100, the new two-step write scheme can increase the array size of CMs 10 times larger than the conventional write. If R RESET/R SET is increased to 500, we can increase the passive array size up to 1000 × 1000 with maintaining the read sensing margin lager than 10% of VDD. The two-step write scheme will be very essential in realizing passive cross-point array without any selection device that is known to be the ideal architecture for future 3-D memories.
  • Keywords
    flash memories; memristors; random-access storage; 3D memories; complementary memristor array; sneak path leakage; write scheme; Arrays; Memristors; Microprocessors; Resistance; Sensors; Switches; Complementary memristor (CM) cell; cross-point memories; memristor; passive memory array; sneak-path leakage; two-step write;
  • fLanguage
    English
  • Journal_Title
    Nanotechnology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1536-125X
  • Type

    jour

  • DOI
    10.1109/TNANO.2012.2188302
  • Filename
    6153382
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1450821