TID-Induced Degradation in Static and Noise Behavior of Sub-100 nm Multifinger Bulk NMOSFETs

Author

Ratti, Lodovico ; Gaioni, Luigi ; Manghisoni, Massimo ; Re, Valerio ; Traversi, Gianluca

Author_Institution

INFN Sezione di Pavia, Pavia, Italy

Volume

58

Issue

3

fYear

2011

fDate

6/1/2011 12:00:00 AM

Firstpage

776

Lastpage

784

Abstract

This paper is concerned with the study of the total ionizing dose (TID) effects in NMOS transistors belonging to 90 and 65 nm CMOS technologies from different manufacturers. Results from static and noise measurements are used to collect further evidence for a static and noise degradation model involving charge buildup in shallow trench isolations and lateral parasitic transistor activation. Comparison between two CMOS processes both belonging to the 90 nm node but coming from different foundries makes it possible to shed some light on the process-dependent features of the device response to ionizing radiation.

Keywords

CMOS integrated circuits; MOSFET; radiation hardening (electronics); semiconductor device noise; TID-induced degradation; ionizing radiation; lateral parasitic transistor activation; multifinger bulk NMOSFET; noise degradation model; noise measurement; shallow trench isolation; size 100 nm; size 65 nm; size 90 nm; static degradation model; static measurement; total ionizing dose effect; Logic gates; MOSFETs; Noise; Radiation effects; Threshold voltage; Ionizing radiation; nanoscale CMOS; noise; shallow trench isolations;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2010.2098046

Filename

5713855