VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm

Author

Kuan, Ta-Wen ; Wang, Jhing-Fa ; Wang, Jia-Ching ; Lin, Po-Chuan ; Gu, Gaung-Hui

Author_Institution

Dept. Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan

Volume

20

Issue

4

fYear

2012

fDate

4/1/2012 12:00:00 AM

Firstpage

673

Lastpage

683

Abstract

The sequential minimal optimization (SMO) algorithm has been extensively employed to train the support vector machine (SVM). This work presents an efficient application specific integrated circuit chip design for sequential minimal optimization. This chip is implemented as an intellectual property core, suitable for use in an SVM-based recognition system on a chip. The proposed SMO chip was tested and found to be fully functional, using a prototype system based on the Altera DE2 board with a Cyclone II 2C70 field-programmable gate array.

Keywords

VLSI; circuit optimisation; electronic engineering computing; field programmable gate arrays; industrial property; integrated circuit design; integrated circuit testing; learning (artificial intelligence); minimisation; support vector machines; Altera DE2 board; Cyclone II 2C70 field programmable gate arrays; SMO chip; SVM learning core; SVM training; SVM-based recognition system; VLSI design; integrated circuit chip design; intellectual property core; sequential minimal optimization algorithm; support vector machine; Algorithm design and analysis; Circuit synthesis; Kernel; Optimization; Support vector machines; Training; Very large scale integration; Field-programmable gate array (FPGA); VLSI design; sequential minimal optimization (SMO); support vector machine (SVM);

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2011.2107533

Filename

5713858