Title :
A cost-effective architecture for HDTV video decoder in ATSC receivers
Author :
Kim, Jeong-Min ; Chae, Soo-lk
Author_Institution :
Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
fDate :
11/1/1998 12:00:00 AM
Abstract :
We describe the architecture of an HDTV video decoder, Vincent5, for MPEG2 MP@HL video decoding and format conversion of all 18 ATSC DTV formats in real-time. Vincent5 adopts a dataflow architecture for its main decoding functions in contrast to the conventional decoders that use a strict pipelined structure. Consequently, this makes it possible for us to explore wide design choices in the architecture decision for each decoding function. In Vincent5 we introduce a new memory control scheme of reducing the memory bandwidth, which is necessary in MPEG2 MP@HL decoding for a cost-effective solution. Without increasing the hardware complexity of Vincent5, we embed three programmable cores into the dedicated hardware to maximize its programmability. Vincent5 was described using the VHDL and its functionality was verified with standard MPEG2 bitstreams. Vincent5 includes 115 K logic gates, 118 Kb RAM, and 32 Kb ROM after logic synthesis and had been fabricated utilizing 3 ML 0.5 μm CMOS technology
Keywords :
CMOS digital integrated circuits; bandwidth compression; data flow computing; decoding; digital signal processing chips; high definition television; television receivers; video coding; 0.5 micron; 118 KByte; 118 kbit; 32 Kbyte; ATSC receivers; CMOS technology; DTV formats; HDTV video decoder; MPEG2 MP@HL decoding; MPEG2 bitstreams; RAM; ROM; VHDL; Vincent5; cost-effective architecture; dataflow architecture; format conversion; logic gates; logic synthesis; memory bandwidth reduction; memory control; programmable cores; Bandwidth; CMOS logic circuits; CMOS technology; Decoding; Digital TV; HDTV; Hardware; Logic gates; Read only memory; Read-write memory;
Journal_Title :
Consumer Electronics, IEEE Transactions on
