U-grooved SIT CMOS technology with 3 fJ and 49 ps (7 mW, 350 fJ) operation

Author

Nishizawa, Jun-ichi ; Takeda, Nobuo ; Suzuki, Sohbe ; Suzuki, Toshifumi ; Tanaka, Tetsu

Author_Institution

Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan

Volume

37

Issue

8

fYear

1990

fDate

8/1/1990 12:00:00 AM

Firstpage

1877

Lastpage

1883

Abstract

Static induction transistor (SIT) CMOS is analyzed by a circuit simulation method. According to the results, the propagation delay time of the SIT CMOS could be represented as the ratio of the load capacitance to the transconductance. The U-grooved structure plays an important role in the fabrication of MOS SIT with large transconductance and small parasitic capacitance. U-grooved SIT CMOS has been fabricated by anisotropic plasma etching, and its switching speed has been evaluated by a 31-stage ring oscillator. A minimum ρ-τ product of 3 fJ/gate has been obtained for a design rule of 1-μm channel length. A minimum propagation delay time of 49 ps/gate has also been obtained at a dissipation power of 7 mW/gate, which corresponds to a ρ-τ product of 350 fJ/gate

Keywords

CMOS integrated circuits; integrated circuit technology; integrated logic circuits; oscillators; 1 micron; 3 fJ; 350 fJ; 49 ps; 7 mW; MOS SIT; SIT CMOS; U-grooved SIT CMOS technology; U-grooved structure; anisotropic plasma etching; channel length; circuit simulation method; design rule; dissipation power; load capacitance; logic circuits; propagation delay time; ring oscillator; small parasitic capacitance; switching speed; transconductance; Anisotropic magnetoresistance; CMOS technology; Circuit analysis; Circuit simulation; Etching; Fabrication; Parasitic capacitance; Plasma applications; Propagation delay; Transconductance;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.57139

Filename

57139