Breaking with tradition in mathematical metal reliability modeling

One of the limiting factors in designing advanced microelectronics is the size and complexity of the wiring used to connect electronic components on a chip. Although transistors can be scaled to smaller sizes with well-understood rules, metallization cannot. Typically, scaling raises the current density as the lines themselves are made thinner. This increases the chance of circuit failure due to electromigration. Another kind of failure that occurs is stress voiding, in which the stresses due to thermal-expansion mismatches of nearby materials and the electromigration of atoms actually break a line. The Motorola Predictive Engineering Laboratory has been developing a computer model for stress and electromigration that includes considerably more physics than the routinely-used statistical models. If we can project metal lifetimes more accurately, we could generate better design rules and thus produce less expensive products that are less limited in area or performance by metallization. We are working directly with engineers who formulate and qualify our metallization processes and extract rules for product designers company-wide. The goal is to affect PowerPC and SmartPower designs