DocumentCode
1451476
Title
Hierarchical diagnosis of identical units in a system
Author
Koppolu, Sasidhar ; Chatterjee, Abhijit
Author_Institution
Intel Corp., Fort Collins, CO, USA
Volume
50
Issue
2
fYear
2001
fDate
2/1/2001 12:00:00 AM
Firstpage
186
Lastpage
191
Abstract
A hierarchical diagnosis algorithm is presented for testing identical units in a system. As all units are similar, it is essential that the test process be parallelized to enable test of multiple units for the cost of testing one unit. With this objective in mind, we propose a novel test architecture consisting of a hierarchy of testers in a system to test all the units simultaneously. In this approach, special test chips are placed at strategic locations in a system to compute a “golden response” by analyzing the responses of all units. The responses are propagated up the hierarchy of testers. At each level, the testers analyze the data and pass golden response computation data to testers at higher level. The tester at the top of the hierarchy computes the golden response and the test result is percolated down to the testers at the lowest level that identify faulty and fault-free units. Using this diagnosis approach, almost all units are correctly diagnosed, even when yields are as low as 40 percent. The hardware architecture of all test chips is identical and simple. This approach can be used for testing massively parallel multiprocessor systems, MCMs fabricated on a large area panel, and integrated circuits on silicon wafers
Keywords
computer debugging; computer testing; fault diagnosis; logic testing; golden response; hierarchical diagnosis; massively parallel multiprocessor systems; test process; testing identical units; Circuit faults; Circuit testing; Computer architecture; Costs; Data analysis; Fault diagnosis; Hardware; Integrated circuit testing; Integrated circuit yield; System testing;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.908994
Filename
908994
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