• DocumentCode
    1452883
  • Title

    Robust RTL power macromodels

  • Author

    Bogliolo, Alessandro ; Benini, Luca

  • Author_Institution
    Dipt. di Elettronica ed Computer Sci., Bologna Univ., Italy
  • Volume
    6
  • Issue
    4
  • fYear
    1998
  • Firstpage
    578
  • Lastpage
    581
  • Abstract
    In this paper, we propose a robust register-transfer level (RTL) power modeling methodology for functional units. Our models are consistently accurate over a wide range of input statistics, they are automatically constructed and can provide pattern-by-pattern power estimates. An additional desirable feature of our modeling methodology is the capability of accounting for the impact of technology variations, library changes and synthesis tools. Our methodology is based on the concept of node sampling, as opposed to more traditional approaches based on input sampling.
  • Keywords
    high level synthesis; low-power electronics; logic circuit; low power design; node sampling; power estimation; register transfer level power macromodel; technology tuning; Circuit simulation; Circuit synthesis; Digital circuits; Energy consumption; Logic; Power dissipation; Robustness; Sampling methods; Software libraries; Statistics;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/92.736131
  • Filename
    736131