DocumentCode
1452919
Title
On circuit clustering for area/delay tradeoff under capacity and pin constraints
Author
Huang, Juinn-Dar ; Jou, Jing-Yang ; Shen, Wen-Zen ; Chuang, Hsien-Ho
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume
6
Issue
4
fYear
1998
Firstpage
634
Lastpage
642
Abstract
In this paper, we propose an iterative area/delay tradeoff algorithm to solve the circuit clustering problem under the capacity constraint. It first finds an initial delay-considered area-optimized clustering solution by a delay-oriented depth first-search procedure. Then, an iterative procedure consisting of several reclustering techniques is applied to gradually trade the area for the performance. We then show that this algorithm can be easily extended to solve the clustering problem subject to both capacity and pin constraints. Experimental results show that our algorithm can provide a complete set of clustering solutions from the area-optimized one to the delay-optimized one for a given circuit. Furthermore, compared to the existing delay-optimized algorithms, this algorithm achieves almost the same performance but with much less area overhead. Therefore, this algorithm is very useful for solving the timing-driven circuit clustering problem.
Keywords
VLSI; delays; integrated circuit design; iterative methods; logic CAD; logic partitioning; VLSI; area overhead; capacity constraints; circuit clustering; delay-oriented depth first-search procedure; iterative area/delay tradeoff algorithm; logic partitioning techniques; pin constraints; reclustering techniques; Circuit synthesis; Clustering algorithms; Delay effects; Integrated circuit interconnections; Iterative algorithms; Joining processes; Logic gates; Partitioning algorithms; Polynomials; Very large scale integration;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/92.736137
Filename
736137
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