DocumentCode :
1453199
Title :
A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel
Author :
Lan, Ying-Cherng ; Lin, Hsiao-An ; Lo, Shih-Hsin ; Hu, Yu Hen ; Chen, Sao-Jie
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume :
30
Issue :
3
fYear :
2011
fDate :
3/1/2011 12:00:00 AM
Firstpage :
427
Lastpage :
440
Abstract :
A bidirectional channel network-on-chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication. In a BiNoC, each communication channel allows to be dynamically self-reconfigured to transmit flits in either direction. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate. Novel on-chip router architecture is developed to support dynamic self-reconfiguration of the bidirectional traffic flow. This area-efficient BiNoC router delivers better performance and requires smaller buffer size than that of a conventional network-on-chip (NoC). The flow direction at each channel is controlled by a channel direction control (CDC) algorithm. Implemented with a pair of finite state machines, this CDC algorithm is shown to be high performance, free of deadlock, and free of starvation. Extensive cycle-accurate simulations using synthetic and real-world traffic patterns have been conducted to evaluate the performance of the BiNoC. These results exhibit consistent and significant performance advantage over conventional NoC equipped with hard-wired unidirectional channels.
Keywords :
finite state machines; network-on-chip; bidirectional channel network-on-chip architecture; buffer size; channel direction control algorithm; communication channel; cycle-accurate simulations; dynamic self-reconfigurable channel; finite state machines; on-chip communication; packet consumption rate; packet delivery latency; real-world traffic patterns; Bandwidth; Computer architecture; Data communication; Protocols; Routing; Switches; System-on-a-chip; Interconnection networks; multiprocessor systems-on-chip (MPSoCs); networks-on-chip (NoCs); on-chip communication; reconfigurable architectures;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2010.2086930
Filename :
5715603
Link To Document :
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