PartMOR: Partitioning-Based Realizable Model-Order Reduction Method for RLC Circuits

This paper presents a robust partitioning-based model-order reduction (MOR) method, PartMOR, suitable for reduction of very large RLC circuits or RLC-circuit parts of a non-RLC circuit. The MOR is carried out on a partitioned circuit, which enables the use of low-order moments and macromodels of few elements, while still preserving good accuracy for the reduction. As the method produces a positive-valued, passive, and stable reduced-order RLC circuit (netlist-in-netlist-out), it can be used in conjunction with any standard analysis tool or circuit simulator without modification. It is shown that PartMOR achieves excellent reduction results in terms of accuracy and reduced CPU time for RLC, RC, and RL circuits.