DocumentCode :
1453231
Title :
Fast heuristic and exact algorithms for two-level hazard-free logic minimization
Author :
Theobald, Michael ; Nowick, Steven M.
Author_Institution :
Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
Volume :
17
Issue :
11
fYear :
1998
fDate :
11/1/1998 12:00:00 AM
Firstpage :
1130
Lastpage :
1147
Abstract :
None of the available minimizers for two-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to manual and automated circuit partitioning techniques. This paper introduces two new two-level hazard-free logic minimizers: ESPRESSO-HF, a heuristic method loosely based on ESPRESSO-II, and IMPYMIN, an exact method based on implicit data structures. Both minimizers can solve all currently available examples, which range up to 32 inputs and 33 outputs. These include examples that have never been solved before. For the more difficult examples that can be solved by other minimizers, our methods are several orders of magnitude faster. As by-products of these algorithms, we also present two additional results. First, we propose a fast new method to check if a hazard-free covering problem can feasibly be solved. Second, we introduce a novel reformulation of the two-level hazard-free logic minimization problem by capturing hazard-freedom constraints within a synchronous function through the addition of new variables
Keywords :
asynchronous circuits; circuit optimisation; data structures; logic CAD; logic partitioning; minimisation of switching nets; ESPRESSO-HF; IMPYMIN; asynchronous design; circuit optimisation; circuit partitioning techniques; hazard-free covering problem; hazard-freedom constraints; implicit data structures; synchronous function; two-level hazard-free logic minimization; Circuit synthesis; Delay; Design automation; Heuristic algorithms; Logic circuits; Logic testing; Manuals; Minimization methods; Packaging; Partitioning algorithms;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.736186
Filename :
736186
Link To Document :
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