An audio ADC Delta-Sigma modulator with 100-dB peak SINAD and 102-dB DR using a second-order mismatch-shaping DAC

Author

Fogelman, E. ; Welz, Jared ; Galton, Ian

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA

Volume

36

Issue

3

fYear

2001

fDate

3/1/2001 12:00:00 AM

Firstpage

339

Lastpage

348

Abstract

A second-order audio analog-to-digital converter (ADC) ΔΣ modulator using a second-order 33-level tree-structured mismatch-shaping digital-to-analog converter (DAC) is presented. Key logic simplifications in the design of the mismatch-shaping DAC encoder are shown which yield the lowest complexity second-order mismatch-shaping DAC known to the authors. The phenomenon of signal-dependent DAC noise modulation in mismatch-shaping DACs is illustrated, and a modified second-order input-layer switching block is presented which reduces inband DAC noise modulation by 6 dB. Implementation details and measured performance of the 3.3-V 0.5-μm single-poly CMOS prototype are presented. All 12 prototype devices achieve better than 100-dB signal-to-noise-and-distortion and 102-dB dynamic range over a 10-20 kHz measurement bandwidth

Keywords

CMOS integrated circuits; analogue-digital conversion; audio signal processing; delta-sigma modulation; digital-analogue conversion; integrated circuit noise; 0.5 micron; 10 to 20 kHz; 3.3 V; CMOS IC; audio analog-to-digital converter; delta-sigma modulator; dynamic element matching; dynamic range; noise modulation; second-order mismatch-shaping digital-to-analog converter; signal-to-noise-and-distortion; tree structure; Analog-digital conversion; CMOS analog integrated circuits; Circuit noise; Delta modulation; Digital modulation; Dynamic range; Noise reduction; Noise shaping; Prototypes; Quantization;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.910472

Filename

910472