An embedded 65 nm CMOS baseband IQ 48 MHz-1 GHz dual tuner for DOCSIS 3.0

Author

Gatta, Francesco ; Gomez, Ray ; Shin, Young ; Hayashi, Takayuki ; Zou, Hanli ; Chang, James Y C ; Dauphinee, Leonard ; Xiao, Jianhong ; Chang, Dave S H ; Chih, Tai-Hong ; Brandolini, Massimo ; Koh, Dongsoo ; Hung, Bryan J J ; Wu, Tao ; Introini, Mattia ;

Volume

48

Issue

4

fYear

2010

fDate

4/1/2010 12:00:00 AM

Firstpage

88

Lastpage

97

Abstract

An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution PLL, and digital image rejection. To our knowledge this is the first reported multichannel broadband tuner embedded in a DOCSIS 3.0 System on a chip implemented in 65 nm pure digital CMOS technology.

Keywords

CMOS integrated circuits; circuit tuning; phase locked loops; surface acoustic wave filters; system-on-chip; CMOS baseband IQ; CMOS digital dual tuner; DOCSIS 3.0; SAW filters; digital image rejection; low-noise high-frequency resolution PLL; multichannel broadband tuner; system on a chip; Active filters; Bandwidth; Baseband; Cable TV; Power cables; Radio frequency; Radio spectrum management; Signal to noise ratio; Tuners; Working environment noise;

fLanguage

English

Journal_Title

Communications Magazine, IEEE

Publisher

ieee

ISSN

0163-6804

Type

jour

DOI

10.1109/MCOM.2010.5439081

Filename

5439081