New low-complexity bit-parallel finite field multipliers using weakly dual bases

New structures of bit-parallel weakly dual basis (WDB) multipliers over the binary ground field are proposed. An upper bound on the size complexity of bit-parallel multiplier using an arbitrary generating polynomial is given. When the generating polynomial is an irreducible trinomial x^m+x^k+1, 1⩽k⩽[m/2], the structure of the proposed bit-parallel multiplier requires only m² two-input AND gates and at most m²-1 XOR gates. The time delay is no greater than T_A+([log₂ m]+2)T_x, where T_A and T_X are the time delays of an AND gate and an XOR gate, respectively