Development of a radiation tolerant 1M SRAM on fully-depleted SOI

Author

Brady, F.T. ; Brown, R. ; Rocket, L. ; Vasquez, J.

Author_Institution

Lockheed Martin Fed. Syst., Manassas, VA, USA

Volume

45

Issue

6

fYear

1998

fDate

12/1/1998 12:00:00 AM

Firstpage

2436

Lastpage

2441

Abstract

1M SRAMs were fabricated on fully-depleted SOI using 0.5 um design rules. The SRAMs were evaluated for speed/power, prompt dose upset, SEE, and total dose hardness. As compared to the identical design fabricated on bulk CMOS, improved results were seen for performance and prompt dose hardness. On the other hand, a low n-channel snapback voltage degraded the standby leakage, total dose hardness, and SEU hardness. The total dose hardness was expectedly low since no attempt was made to harden the buried oxide for this evaluation. This effort reflects the most complicated circuit reported on fully-depleted SOI

Keywords

CMOS memory circuits; SRAM chips; radiation hardening (electronics); silicon-on-insulator; 0.5 micron; 1 Mbit; CMOS SRAM; SEE; SEU hardness; buried oxide; fully depleted SOI; power; prompt dose upset; radiation tolerance; snapback voltage; speed; standby leakage; total dose hardness; CMOS process; CMOS technology; Circuits; Design optimization; Dielectric substrates; Doping; Radiation hardening; Random access memory; Silicon; Single event upset;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.736483

Filename

736483