Impact of ion energy on single-event upset

Author

Dodd, P.E. ; Musseau, O. ; Shaneyfelt, M.R. ; Sexton, F.W. ; D´hose, C. ; Hash, G.L. ; Martinez, M. ; Loemker, R.A. ; Leray, Jean-Luc ; Winokur, P.S.

Author_Institution

Sandia Nat. Labs., Albuquerque, NM, USA

Volume

45

Issue

6

fYear

1998

fDate

12/1/1998 12:00:00 AM

Firstpage

2483

Lastpage

2491

Abstract

The impact of ion energy on single-event upset was investigated by irradiating CMOS SRAMs with low and high-energy heavy ions. A variety of CMOS SRAM technologies was studied, with gate lengths ranging from 1 to 0.5 μm and integration densities from 16 Kbit to 1 Mbit. No significant differences were observed between the low and high-energy single-event upset response. The results are consistent with simulations of heavy-ion track structures that show the central fore of the track structures are nearly identical for low and high-energy ions. Three-dimensional simulations confirm that charge collection is similar in the two cases. Standard low-energy heavy ion tests are more cost-effective and appear to be sufficient for CMOS technologies down to 0.5 μm. We discuss implications for deep submicron scaling, multiple-bit upsets, and hardness assurance

Keywords

CMOS memory circuits; SRAM chips; ion beam effects; 1 to 0.5 micron; 16 Kbit to 1 Mbit; CMOS SRAM; deep submicron scaling; hardness assurance; heavy ion irradiation; ion energy; ion track; multiple bit upset; single event upset; three-dimensional simulation; CMOS technology; Circuit testing; Cyclotrons; Ion accelerators; Iron; Laboratories; Life estimation; Particle accelerators; Performance evaluation; Single event upset;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.736489

Filename

736489