DocumentCode
1455601
Title
Three-Dimensional Wafer Stacking Using Cu–Cu Bonding for Simultaneous Formation of Electrical, Mechanical, and Hermetic Bonds
Author
Tan, Chuan Seng ; Peng, Lan ; Fan, Ji ; Li, Hongyu ; Gao, Shan
Author_Institution
Nanyang Technol. Univ., Singapore, Singapore
Volume
12
Issue
2
fYear
2012
fDate
6/1/2012 12:00:00 AM
Firstpage
194
Lastpage
200
Abstract
Wafer-on-wafer stacking is demonstrated successfully using bumpless Cu-Cu bonding for the simultaneous formation of electrical connection, mechanical support, and hermetic frame for 3-D IC application. The ohmic behavior of the Cu-Cu bond is verified. A daisy chain of at least 44 000 contacts at a 15-μm pitch is connected successfully and sustains thermal cycling. Postbonding delamination is found to be strongly affected by the wafer curvature and bond strength. The Cu-Cu hermetic seal ring shows a helium leak rate more than ten times lower than the reject limit (5 × 10-8 atm · cm/s based on MIL-STD-883E standard) without underfill. This provides a robust IC-to-IC connection density of 4.4 × 105 cm-2, suitable for future wafer-level 3-D integration.
Keywords
delamination; integrated circuit bonding; three-dimensional integrated circuits; wafer bonding; 3D IC application; Cu-Cu; Postbonding delamination; electrical connection; hermetic bond formation; mechanical support; robust IC-to-IC connection density; size 15 mum; thermal cycling; three-dimensional wafer stacking; wafer-level 3D integration; wafer-on-wafer stacking; Bonding; Contact resistance; Copper; Rough surfaces; Silicon; Surface roughness; Surface treatment; Cu–Cu bonding; hermetic seal; three-dimensional integrated circuit (3-D IC);
fLanguage
English
Journal_Title
Device and Materials Reliability, IEEE Transactions on
Publisher
ieee
ISSN
1530-4388
Type
jour
DOI
10.1109/TDMR.2012.2188802
Filename
6156757
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