Dependence of DC Parameters on Layout and Low-Frequency Noise Behavior in Strained-Si nMOSFETs Fabricated by Stress-Memorization Technique

Author

Huang, Yao-Tsung ; Wu, San Lein ; Chang, Shoou Jinn ; Kuo, Cheng Wen ; Chen, Ya Ting ; Yao-Chin Cheng ; Cheng, Yao-Chin

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Volume

31

Issue

5

fYear

2010

fDate

5/1/2010 12:00:00 AM

Firstpage

500

Lastpage

502

Abstract

The impact of stress-memorization technique (SMT)-induced tensile strain on the layout dependence of nMOSFET characteristics is investigated. It is found that the incorporation of the SMT process provides up to 12% improvement in transconductance and 9% enhancement in on-state current for nMOSFETs with a source/drain length (L_S/D) of 1.76 ??m and W = 0.5 ??m. The characteristics of the SMT device become more sensitive to the layout geometry as L_S/D and W are down to 0.5 and 0.25 ??m, respectively. Moreover, low-frequency measurements reveal that the interface quality of the SMT device is the same as that of the control devices. Furthermore, it is found that the mechanism of 1/f noise in the SMT device can be properly interpreted by the unified model.

Keywords

MOSFET; elemental semiconductors; silicon; DC parameters; ON-state current; Si; low-frequency noise behavior; size 0.25 mum; size 0.5 mum; size 1.76 mum; strained nMOSFET; stress-memorization technique; Layout geometry; low frequency; stress-memorization technique (SMT); unified model;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2010.2044477

Filename

5439695