Low-power state assignment targeting two- and multilevel logic implementations

Author

Tsui, Chi-ying ; Pedram, Massoud ; Despain, Alvin M.

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Clear Water Bay, Hong Kong

Volume

17

Issue

12

fYear

1998

fDate

12/1/1998 12:00:00 AM

Firstpage

1281

Lastpage

1291

Abstract

The problem of minimizing power consumption during the state encoding of a finite-state machine is addressed. A new power cost model for state encoding is proposed, and encoding techniques that minimize this power cost for two- and multilevel logic implementations are described. These techniques are compared with those that minimize area or the switching activity at the present state bits. Experimental results show significant improvements

Keywords

finite state machines; logic design; low-power electronics; minimisation of switching nets; multivalued logic circuits; state assignment; area; finite state machine; low power state assignment; minimization; multilevel logic; power consumption; power cost model; state encoding; switching activity; two-level logic; Circuit simulation; Computational modeling; Costs; Electronic circuits; Encoding; Energy consumption; Hypercubes; Logic; Minimization; Simulated annealing;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.736568

Filename

736568