Title :
Random pattern testability of memory address logic
Author_Institution :
New Jersey Inst. of Technol., Newark, NJ, USA
fDate :
12/1/1998 12:00:00 AM
Abstract :
An analytical method is described for determining the random pattern testability of faults in combinational logic feeding the address inputs of embedded memories. Difference information from replicated copies of embedding logic is used to determine the probability of detecting any fault in the upstream of either a read or write port address decoder. The method can be used with minor extensions to existing detection probability tools such as the cutting algorithm
Keywords :
built-in self test; combinational circuits; fault diagnosis; integrated circuit testing; integrated memory circuits; logic testing; probability; BIST; combinational logic; cutting algorithm; detection probability tools; embedded memories; fault detection; memory address logic; probability; random pattern testability; read port address decoder; write port address decoder; Built-in self-test; Computational modeling; Fault detection; Feeds; Hardware; Jacobian matrices; Logic arrays; Logic design; Logic testing; Random access memory;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
