DocumentCode :
1455826
Title :
Retiming DAGs [direct acyclic graph]
Author :
Calland, P.Y. ; Mignotte, A. ; Peyran, O. ; Robert, Y. ; Vivien, F.
Author_Institution :
Lab. LIP-IMAG, Ecole Normale Superieure de Lyon, France
Volume :
17
Issue :
12
fYear :
1998
fDate :
12/1/1998 12:00:00 AM
Firstpage :
1319
Lastpage :
1325
Abstract :
This paper is devoted to a low-complexity algorithm for retiming circuits without cycles, i.e., those whose network graph is a direct acyclic graph (DAG). On one hand, DAGs have a great practical importance, as shown by the on-line arithmetic circuits used as a target application in this paper. On the other hand, retiming is a costly design optimization technique, in particular when applied to large circuits. Hence the need to design a specialized retiming algorithm to handle DAGs more efficiently than general-purpose retiming algorithms. Our algorithm dramatically improves on current solutions in the literature. We gain an order of magnitude in the worst case complexity, and we show convincing experimental results at the end of this paper
Keywords :
VLSI; circuit CAD; circuit optimisation; computational complexity; digital arithmetic; digital integrated circuits; graph theory; logic CAD; timing; circuit retiming; design optimization technique; direct acyclic graph; low-complexity algorithm; network graph; online arithmetic circuits; specialized retiming algorithm; Algorithm design and analysis; Arithmetic; Circuits; Clocks; Cost function; Design optimization; Pipeline processing; Polynomials; Registers; Very large scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.736571
Filename :
736571
Link To Document :
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