Title :
Techniques for minimizing power dissipation in scan and combinational circuits during test application
Author :
Dabholkar, Vinay ; Chakravarty, Sreejit ; Pomeranz, Irith ; Reddy, Sudhakar
Author_Institution :
Silicon Autom. Syst., India
fDate :
12/1/1998 12:00:00 AM
Abstract :
Reduction of power dissipation during test application is studied for scan designs and for combinational circuits tested using built-in self-test (BIST). The problems are shown to be intractable. Heuristics to solve these problems are discussed. We show that heuristics with good performance bounds can be derived for combinational circuits tested using BIST. Experimental results show that considerable reduction in power dissipation can be obtained using the proposed techniques
Keywords :
VLSI; built-in self test; combinational circuits; integrated circuit testing; integrated logic circuits; logic testing; minimisation; BIST; built-in self-test; combinational circuits; heuristics; performance bounds; post-ATPG phase; power dissipation minimisation; scan designs; test application; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit synthesis; Circuit testing; Combinational circuits; Minimization; Packaging; Power dissipation; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
