Computation of Error Resiliency of Muller C-element

Error resiliency, which signifies the capability of a circuit to tolerate errors and produce correct outputs, assumes greater significance for digital design in the nanoscale regime due to the relentless miniaturization of semiconductor devices. In this context, the self-timed design paradigm forms an attractive and viable alternative for the VLSI design community. In this paper, the error resiliency of a predominantly used asynchronous logic primitive viz. The Muller C-element is estimated and compared alongside the error resiliencies of combinational logic primitives. The probabilistic analysis reveals that the Muller C-element has good error tolerance similar to that of AND, NAND, OR and NOR gates, and features superior error immunity compared to XOR and XNOR gate types.