A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design

Author

Kawai, Kenji ; Koike, Keiichi ; Takei, Yuichiro ; Onozawa, Akira ; Obara, Hitoshi ; Ichino, Haruhiko

Author_Institution

NT Optical Network Syst., Kanagawa, Japan

Volume

34

Issue

1

fYear

1999

fDate

1/1/1999 12:00:00 AM

Firstpage

12

Lastpage

17

Abstract

A regenerator-section terminating digital large-scale-integration chip for an STM-16 (2.5-Gbit/s synchronous optical network/synchronous digital hierarchy) regenerator has been developed using low-power bipolar technologies. The high-speed performance of bipolar devices enabled four or more chips, including a demultiplexer and a multiplexer, to be integrated into a single chip. The low-power dissipation of 557 mW, only about one-tenth that of previously reported chips, was achieved through the use of four design steps: one-chip integration architecture, power management, 2.5-V emitter-coupled logic, and power optimization

Keywords

SONET; bipolar digital integrated circuits; emitter-coupled logic; high-speed integrated circuits; large scale integration; low-power electronics; optical repeaters; synchronous digital hierarchy; 2.5 Gbit/s; 2.5 V; 557 mW; SONET/SDH regenerator section termination; demultiplexer; emitter coupled logic; low power high speed bipolar digital LSI chip; multiplexer; one-chip integration architecture; power management; power optimization; synchronous digital hierarchy; synchronous optical network; Circuits; Energy management; Laboratories; Large scale integration; Power dissipation; Repeaters; SONET; Synchronous digital hierarchy; WDM networks; Wavelength division multiplexing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.736651

Filename

736651