Automating Interconnect Organization for Minimizing Dynamic Power in SoC

In modern circuits, the impact of interconnect circuitry on dynamic power consumption grows enormous. The functional unit duplication (FUD) with isolation can eliminate interconnect overhead. However, the FUD usually causes massive increase of area and isolation cost. Thus, designers should carefully apply the FUD to achieve the least dynamic power consumption considering a cost budget. We propose an algorithm to automate the process for deriving the optimal organization of FUs.