DocumentCode :
1457458
Title :
Static Test Data Volume Reduction Using Complementation or Modulo- M Addition
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume :
19
Issue :
6
fYear :
2011
fDate :
6/1/2011 12:00:00 AM
Firstpage :
1108
Lastpage :
1112
Abstract :
Both test compaction and test data compression methods provide an opportunity for a tester to apply modified versions of each test, in addition to the original test. We take advantage of this opportunity to achieve additional test data volume reductions. One way to modify a test is to complement some or all of its bits. We represent the way in which modified tests will be obtained by a complementation vector. Experimental results demonstrate that, even when a test set has minimum or close-to-minimum size, the use of a complementation vector allows us to reduce the size of the stored test set further, and almost always below the known lower bound on the size of a test set. The use of a complementation vector is equivalent to a modulo-2 addition operation. We generalize it to modulo- M addition, for a constant M ≥ 2. With modulo-M addition, each stored test yields up to M tests. It is thus possible to reduce the size of the stored test set even further.
Keywords :
data compression; digital arithmetic; logic testing; complementation vector; modulo-2 addition operation; modulo-M addition; static test data volume reduction; test compaction method; test data compression method; Circuit faults; Circuit testing; Compaction; Electrical fault detection; Encoding; Fault detection; Helium; Logic circuits; Logic testing; Test data compression; Scan circuits; static test compaction; stuck-at faults; test data compression;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2010.2044819
Filename :
5439944
Link To Document :
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