DocumentCode
1457920
Title
Substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel SOI MOSFET´s
Author
Maeda, Shigenobu ; Hirano, Yuuichi ; Yamaguchi, Yasuo ; Iwamatsu, Toshiaki ; Ipposhi, Takashi ; Ueda, Kimio ; Mashiko, Koichiro ; Maegawa, Shigeto ; Abe, Haruhiko ; Nishimura, Tadashi
Author_Institution
ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
Volume
46
Issue
1
fYear
1999
fDate
1/1/1999 12:00:00 AM
Firstpage
151
Lastpage
158
Abstract
The substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFET´s) were investigated. Here, “substrate bias” is the body bias in the SOI MOSFET itself. It was found that the transistor body becomes fully depleted and the transistor is released from the substrate-bias effect, when the body is reverse-biased. Moreover, it was found that the source-drain breakdown voltage for reverse-bias is as high as that for zero-bias. This phenomenon was analyzed using a three-dimensional (3-D) device simulation considering the body-tied SOI MOSFET structure in which the body potential is fixed from the side of the transistor. This analysis revealed that holes which are generated in the transistor are effectively pulled out to the body electrode, and the body potential for reverse-bias remains lower than that for zero-bias, and therefore, the source-drain breakdown characteristics does not deteriorate for reverse-bias. Further, the influence of this effect upon circuit operation was investigated. The body-tied configuration of SOI devices is very effective in exploiting merits of SOI and in suppressing the floating body-effect, and is revealed to be one of the most promising candidates for random logic circuits such as gate arrays and application specific integrated circuits
Keywords
MOSFET; semiconductor device breakdown; silicon-on-insulator; body potential; body-tied short-channel SOI MOSFET; floating body effect; random logic circuit; source-drain breakdown; substrate bias; three-dimensional device simulation; Analytical models; Character generation; Electric breakdown; Electrodes; FETs; Logic arrays; Logic circuits; MOSFET circuits; Semiconductor device breakdown; Silicon on insulator technology;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.737454
Filename
737454
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