DocumentCode
1458021
Title
Design considerations of high-κ gate dielectrics for sub-0.1-μm MOSFET´s
Author
Cheng, Baohong ; Cao, Min ; Vande Voorde, Paul ; Greene, Wayne ; Stork, Hans ; Yu, Zhiping ; Woo, Jason C S
Author_Institution
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Volume
46
Issue
1
fYear
1999
fDate
1/1/1999 12:00:00 AM
Firstpage
261
Lastpage
262
Abstract
The potential impact of high-κ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities. It is shown that the short-channel performance degradation caused by the fringing fields from the gate to the source/drain regions, is mainly determined by the gate thickness-to-length aspect ratio. In addition, the gate stack configuration also plays an important role in the determination of the device short-channel performance degradation
Keywords
MOSFET; dielectric thin films; permittivity; 0.1 micron; MOSFET; aspect ratio; design; fringing field; gate dielectric; permittivity; short channel device; Degradation; Dielectric devices; Dielectric materials; Dielectric substrates; Laboratories; MOSFET circuits; Medical simulation; Permittivity; Semiconductor device doping; Tunneling;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.737469
Filename
737469
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