Design and analysis of multi-level n-to-2n decoders in CMOS technology

This paper presents designs and analysis of n-to-2ⁿ - lines decoders created using fast and efficient method. Thanks to especially designed building blocks a decoder of any size can be built in easy way. Layouts of all needed fundamental blocks were designed in UMC 180 CMOS technology, as standard cells. A few layouts of decoders were designed as one and multi-level structures and their parameters such as energy, time, and area were assessed. Power consumption were considered under extended model, which takes into account changes of input vectors, not only switching activity factor. Thanks to these analyses some interesting and important conclusions are derived.