Title :
High-Speed Low-Power True Single-Phase Clock Dual-Modulus Prescalers
Author :
Chen, Wu-Hsin ; Jung, Byunghoo
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fDate :
3/1/2011 12:00:00 AM
Abstract :
A new design technique that improves operating speed of true single-phase clock-based (TSPC) prescalers is presented. We implement dual-modulus prescalers without using any extra logic gates by exploiting the behavior of the second branch in a TSPC flip-flop. The proposed design technique is applied to ÷2/3 and ÷3/4 prescalers, and their performances are compared with previous work. Implemented in a 130-nm CMOS technology and compared at same process-voltage-temperature conditions, the maximum speed of the ÷2/3 prescaler reaches 88% of the maximum operating frequency of a single TSPC flip-flop, and the ÷3/4 prescaler reaches 75%. In addition, the proposed divide-by-3 prescaler is able to work almost at the speed of the single TSPC flip-flop. A frequency divider that provides dividing ratios of 7, 8, and 9 is implemented as a part of a 3.4-5-GHz integer- N phase-locked loop in a 130-nm CMOS technology. Simulation and measurement results demonstrate high-speed, low-power, and multiple division ratio capabilities of the proposed technique.
Keywords :
CMOS logic circuits; flip-flops; frequency dividers; logic design; logic gates; low-power electronics; phase locked loops; prescalers; CMOS technology; TSPC flip-flops; divide-by-3 prescaler; division ratio; frequency 3.4 GHz to 5 GHz; frequency divider; logic gates; phase locked loop; size 130 nm; true single-phase clock dual-modulus prescalers; Clocks; Delay; Frequency conversion; Frequency measurement; Logic gates; Power demand; Transistors; Dual modulus; frequency divider; prescaler; true single-phase clocked (TSPC) logic;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2011.2106351
