A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme

Author

Miura, Noriyuki ; Shidei, Tsunaaki ; Yuan, Yuxiang ; Kawai, Shusuke ; Takatsu, Keita ; Kiyota, Yuji ; Asano, Yuichi ; Kuroda, Tadahiro

Author_Institution

Keio Univ., Yokohama, Japan

Volume

46

Issue

4

fYear

2011

fDate

4/1/2011 12:00:00 AM

Firstpage

965

Lastpage

973

Abstract

This paper presents a 10 fJ/bit inductive-coupling data link operating at 0.55 V supply voltage and a 135 fJ/cycle clock link at 0.7 V supply voltage. A dual-coil transmission scheme reduces the number of stacked transistors in a transmitter, enabling low-voltage and hence low-power operation. A test chip is fabricated in 65 nm CMOS whose nominal supply voltage is 1.2 V. A data rate of 1.1 Gb/s and a clock rate of 3.3 GHz, both with an error rate <; 10^-12, are achieved at 0.55 V and 0.7 V supply voltage, respectively.

Keywords

CMOS digital integrated circuits; clocks; low-power electronics; CMOS; bit rate 1.1 Gbit/s; clock link; dual-coil transmission scheme; frequency 3.3 GHz; inductive-coupling data link; low-power operation; low-voltage operation; size 65 nm; voltage 0.55 V; voltage 0.7 V; voltage 1.2 V; Clocks; Coils; Driver circuits; Energy dissipation; Receivers; Transistors; Transmitters; Inductive coupling; chip stacking; low power; three dimensional;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2011.2108127

Filename

5720524