Continuous-time feedback in floating-gate MOS circuits

Author

Hasler, Paul

Author_Institution

Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

Volume

48

Issue

1

fYear

2001

fDate

1/1/2001 12:00:00 AM

Firstpage

56

Lastpage

64

Abstract

We present the negative- and positive-feedback circuit configurations of continuous-time floating-gate MOS circuits. We start by reviewing the dynamics of our pFET and nFET single-transistor synapses. We present the range of possible stabilizing and destabilizing types of feedback in circuits with one floating-gate synapse, including data from nFET and pFET synapses. We then show examples of competitive and cooperative behavior in multiple-synapse circuits. We present experimental data from circuits fabricated in the 2-μm n-well CMOS process available through MOSIS. We see similar experimental effects in 1.2and 0.5-μm processes

Keywords

CMOS analogue integrated circuits; analogue processing circuits; circuit feedback; continuous time systems; hot carriers; neural chips; 0.5 micron; 1.2 micron; 2 micron; MOSIS; continuous-time feedback; floating-gate MOS circuits; multiple-synapse circuits; n-well CMOS process; nFET synapses; negative-feedback circuit configurations; pFET synapses; positive-feedback circuit configurations; single-transistor synapses; CMOS process; Coupling circuits; Dynamic programming; Feedback circuits; Nonvolatile memory; Secondary generated hot electron injection; Semiconductor device modeling; Silicon; Tunneling; Voltage;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.913187

Filename

913187