DocumentCode
1459940
Title
Correlation learning rule in floating-gate pFET synapses
Author
Hasler, Paul ; Dugger, Jeff
Author_Institution
Integrated Comput. Electron. Lab., Georgia Inst. of Technol., Atlanta, GA, USA
Volume
48
Issue
1
fYear
2001
fDate
1/1/2001 12:00:00 AM
Firstpage
65
Lastpage
73
Abstract
We study the weight dynamics of the floating-gate pFET synapse and the effects of the pFET´s gate and drain voltages on these dynamics. We show that we can derive a weight update rule such that the equilibrium weight value is proportional to the correlation between the gate and drain voltages. In particular, we want a rule of the form τ´ ΔW˙=-ΔW+ηE[xy], where x is a voltage signal on the gate terminal and y is a voltage signal on the drain terminal. We obtain this rule by making a linear approximation to the weight dynamics around a given equilibrium point. We develop this approximation by considering the basic functional form of the system dynamics and then examining the effects of the gate and drain voltages on the specifics of this form
Keywords
CMOS analogue integrated circuits; analogue processing circuits; hot carriers; learning (artificial intelligence); neural chips; correlation learning rule; drain voltages; equilibrium weight value; floating-gate pFET synapses; gate voltages; linear approximation; system dynamics; weight dynamics; weight update rule; Analog computers; Circuits; Computer networks; Linear approximation; MOS capacitors; Neural networks; Nonvolatile memory; Secondary generated hot electron injection; Tunneling; Voltage;
fLanguage
English
Journal_Title
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher
ieee
ISSN
1057-7130
Type
jour
DOI
10.1109/82.913188
Filename
913188
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