PVT Variation Tolerant Current Source With On-Chip Digital Self-Calibration

Author

Moo-Young Kim ; Hokyu Lee ; Chulwoo Kim

Author_Institution

Electr. & Electron. Eng. Dept., Korea Univ., Seoul, South Korea

Volume

20

Issue

4

fYear

2012

fDate

4/1/2012 12:00:00 AM

Firstpage

737

Lastpage

741

Abstract

A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is self-calibrated digitally by an on-chip digital PVT detector, a current error of only ±2% is achieved. The current source has been implemented in an 80-nm CMOS process, occupies 0.018 mm² and consumes 94.9 μW at a supply voltage of 1.0 V.

Keywords

CMOS digital integrated circuits; calibration; constant current sources; CMOS process; PVT variation tolerant current source; current error; nMOS array on-resistance; on-chip digital PVT detector; on-chip digital self-calibration; power 94.9 muW; power consumption; process-supply voltage-temperature variations; size 80 nm; voltage 1.0 V; Arrays; Clocks; Delay; Detectors; MOS devices; Power demand; Resistors; All digital gates; current source; on-chip; process, supply voltage, and temperature (PVT) detector; self-calibration;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2011.2109971

Filename

5720543