Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

This paper presents a vertical gate-all-around nanowire FET (VFET) architecture targeting 5nm and beyond technologies, and a new standard-cell construct for digital flow implementation. VFET technology circuits and parasitics for processes and design features aligned with 5nm CMOS are systematically assessed for the first time. Self-aligned quadruple pattering (SAQP) is implemented to achieve required 12nm half-pitch interconnects, and the worst case RC delay corner is 1.4X slower than best case corner. Our work shows that interconnect delay variability of a wire of average length in SoCs can overwhelm device variability. Consequently, a new device architecture with a smaller footprint as VFET would effectively lower the BEOL variability by shortening the wirelength and help SRAM bit cells to follow 50% area scaling trend. It is shown that a VFET-based D Flip-Flop (DFF) and 6T-SRAM cell can offer 30% smaller layout area than FinFET (or equivalent lateral 2D) based designs. Furthermore, we obtain a 19% reduction in routing area of a 32-bit multiplier implemented with a VFET-based standard-cell library w.r.t. the FinFET design.