DocumentCode
1460276
Title
Word-Based Montgomery Modular Multiplication Algorithm for Low-Latency Scalable Architectures
Author
Shieh, Ming-Der ; Lin, Wen-Ching
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Volume
59
Issue
8
fYear
2010
Firstpage
1145
Lastpage
1151
Abstract
Modular multiplication is a crucial operation in public key cryptosystems like RSA and elliptic curve cryptography (ECC). This paper presents a new word-based Montgomery modular multiplication algorithm which can be used to achieve a low-latency scalable architecture for efficient hardware implementations. We show how to relax the data dependency in conventional word-based algorithms so that a latency of exactly one cycle can be obtained regardless of the chosen word size w (w > 1). With the presented operand reduction scheme, the proposed scalable architecture can operate at high speeds and suitable data paths can be chosen for specific applications. Complexity analysis shows that the proposed architecture has the lowest latency and area complexity compared to related scalable architectures. Experimental results demonstrate that our design has area, speed, and flexibility advantages over related schemes.
Keywords
Application software; Computer architecture; Data communication; Digital arithmetic; Elliptic curve cryptography; Galois fields; Hardware; Propagation delay; Public key cryptography; Very large scale integration; Algorithms implemented in hardware; VLSI.; computations in finite fields; computer arithmetic; high-speed arithmetic;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.2010.72
Filename
5441286
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