Title :
A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique
Author :
Sung-Ho Wang ; Kim, Jeongpyo ; Lee, Joonsuk ; Nam, Hyoung Sik ; Kim, Young Gon ; Shim, Jae Hoon ; Ahn, Hyung Ki ; Kang, Seok ; Jeong, Bong Hwa ; Ahn, Jin Hong ; Kim, Beomsup
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
fDate :
4/1/2001 12:00:00 AM
Abstract :
A quadruple data rate (QDR) synchronous DRAM (SDRAM) interface processing data at 500 Mb/s/pin with a 125-MHz external clock signal is presented. Since the QDR interface has a narrower data timing window, a precise skew control on data signals is required. A salient skew cancellation technique with a shared skew estimator is proposed. The skew cancellation circuit not only reduces the data signal skews on a printed circuit board down to 250 ps, but also aligns the data signals with an external clock signal. The entire interface, fabricated in a 0.35-μm CMOS technology, includes a high-speed data pattern generator and consumes 570 mW of power at 3.0-V supply. The active die area of the chip with the on-chip data pattern generator is 2.4 mm2
Keywords :
DRAM chips; delay lock loops; memory architecture; phase locked loops; storage management chips; synchronisation; 0.35 micron; 125 MHz; 250 ps; 3.0 V; 500 Mbit/s; 570 mW; QDR interface; active die area; data timing window; external clock signal; high-speed data pattern generator; on-chip data pattern generator; printed circuit board; quadruple data rate SDRAM interface; shared skew estimator; skew cancellation technique; CMOS technology; Clocks; Microprocessors; Phase locked loops; Power generation; Printed circuits; Random access memory; SDRAM; Signal processing; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
