The impact of intrinsic device fluctuations on CMOS SRAM cell stability

Author

Bhavnagarwala, Azeez J. ; Tang, Xinghai ; Meindl, James D.

Author_Institution

Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA

Volume

36

Issue

4

fYear

2001

fDate

4/1/2001 12:00:00 AM

Firstpage

658

Lastpage

665

Abstract

Reductions in CMOS SRAM cell static noise margin (SNM) due to intrinsic threshold voltage fluctuations in uniformly doped minimum-geometry cell MOSFETs are investigated for the first time using compact physical and stochastic models. Six sigma deviations in SNM due to intrinsic fluctuations alone are projected to exceed the nominal SMM for sub-100-nm CMOS technology generations. These large deviations pose severe barriers to scaling of supply voltage, channel length, and transistor count for conventional 6T SRAM-dominated CMOS ASICs and microprocessors

Keywords

CMOS memory circuits; SRAM chips; application specific integrated circuits; circuit stability; integrated circuit modelling; integrated circuit noise; ASICs; CMOS; SRAM cell stability; channel length; intrinsic device fluctuations; intrinsic fluctuations; intrinsic threshold voltage fluctuations; physical models; static noise margin; stochastic models; supply voltage; transistor count; uniformly doped minimum-geometry cell MOSFETs; CMOS technology; Fluctuations; MOSFETs; Microprocessors; Noise reduction; Random access memory; Semiconductor device modeling; Six sigma; Stochastic resonance; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.913744

Filename

913744